Greater levels of integration have been the tools of the trade to progress the performance and functionality of computing platforms of any type, achieving the goals of lowering power, complexity, and cost by increasing efficiency. On that note, among many problems, one crucial part hasn’t received enough attention yet — the clock timing solutions. Nevertheless, this is about to change with the advent of the SiTime Chorus family of clock generators geared towards complementing the swift lane of AI data centers and networking technologies.
Integrated timing solution
Advanced devices, in almost all cases, are equipped with time-clocking circuits. They are part of any up-to-date workstation or server design specification list. They essentially are an engine within the processor, delivering core kHz levels while staying in sync among data flow and other circuit segments. In the past, complicated circuits have used different types of delays, such as resonators and oscillators, to work as clock sources and clog the buffers and the generators. These are responsible for clock duplication, division, and multiplication.
Sitar’s advantage of integrating all these technologies in a single device, with its incorporation of Aura’s clock synthesis technology and SiTime MEMS resonator-based technology, has virtually eliminated the clocking timing solution hierarchy as previously, where one system-on-chip device needed an independent clock source for each processor and input and output interfaces.
Simplifying AI data center clocking
With the help of SiTime Chorus clock generators, the shifting clock hierarchy level is now an image. In other words, the entire timing solution for this simplified circuit design is now present in a single SiTime Chorus clock generator, accelerating the reduction of board complexities and area use and lessening the power consumption of the components. In addition, multiple failure risks are also minimized. SiTime claims all three traits to be provided by Chorus, possibly each in a single, 4mm x 4mm package: this translates to up to 10X better resilience, excellent stability, and lower phase jitter (clock deviation).
This latter works as well as enlarging the clock timing design capacity of engineers because aroused Chorus clock generators are 6 weeks earlier than similar products market introduction time. “AI makes datacenters require more data throughput and thus uses less power. SiTime can help resolve this issue as it is well positioned and knows the market variables”. “The timeline of takt via hard farmers was characterized by pain about usages of discrete product types, e.g., the clocks, oscillators, and resonators, and this created performance compromises. The chorus delivers the integrator clock generator to solve such problems, and it’s another example of us transforming the timing market with our unique approach.”
SiTime is evolving and expanding its market presence by aiming Chorus at key AI Data Center applications such as Smart NICs, PAM-4 boards at 400 – 800 Gbps high-speed communication links, and data center enterprise switching.
SiTime’s line, the Chorus series of clock generators, is now being sampled for strategic customers, with Gen. sampling available in the year’s second half. All software system designers who need highly accurate timing solutions that are greener, more dependable, yet fully integrated into their designs will see Chorus as a win-win.
This article originally appeared in Forbes.
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